The present invention relates in general to data communication using parallel access data streams, and more specifically, to methods, systems and computer program products for parallel access data stream communication in distributed shared memory systems having a variable latency.
A central processing unit (CPU) cache is a cache used by a computer CPU to reduce the average time to access data from main memory. A cache is memory, smaller and faster than main memory, which stores copies of data from frequently used main memory locations. A cache is often organized as a hierarchy of cache levels such as a level 1 cache (L1), a level 2 cache (L2), a level 3 cache (L3) and so on. When the CPU needs to access a location in main memory, the CPU first checks whether a copy of that data is in the cache. If the data exist in the cache, the processor reads from or writes to the cache, which is faster than reading from or writing to main memory.
Each cache holding data associated with a location in main memory presents a potential data coherency problem. For example, the relevant data in main memory may be changed by other entities (for example, by peripherals using DMA (direct memory access) or by any of the various cores in a multi-core processor), in which case the copy in the cache(s) may become stale (out-of-date). Alternatively, when a CPU in a multiprocessor system updates data in an associated cache, copies of that data in caches associated with other CPUs become stale.